Duty analysis system for a semiconductor integrated circuit and duty analysis method of the same

ABSTRACT

A system for analyzing a monolithic integrated circuit includes a logic circuit simulator configured to obtain a cell duty of a primitive cell configuring a logic circuit by performing a logic simulation of the logic circuit based on a netlist of the logic circuit and input vectors for the logic circuit, an analog circuit simulator configured to obtain a transistor duty of a transistor that configures a primitive cell by performing an analog simulation of the primitive cell based on a netlist of the analog circuit of the primitive cell and input vectors for the primitive cell, and a synthesis module configured to obtain a synthesized duty of a transistor of the logic circuit by performing a synthesis of the cell and transistor duties.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application P2001-305706 filed on Oct. 1,2001; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an analysis system for asemiconductor integrated circuit and an analysis method of the same,which finds the duty of a transistor in a large-scale logic circuitusing an analog circuit simulator and a logic circuit simulator.

[0004] 2. Description of the Related Art

[0005] In the design stage of a semiconductor integrated circuit, thereare many cases where the duty of a transistor—the element activationrate or the bias transition probability of the transistor—is required,with the duty of a transistor mainly being required when analyzingproblems in reliability. Here, the duty of the transistor means thepercentage which the transistor is at a certain predetermined biasstatus within a certain specified period of time. The specified biasstatus is arbitrarily defined in accordance with the details that are tobe analyzed.

[0006] Conventionally, to find the duty of the transistor, there is amethod whereby the duty of the transistor is obtained by performing asimulation using an analog circuit simulator such as that typified byHSPICE or the like, and then by analyzing the circuit dynamically.Although this method may be applicable for a circuit havingapproximately 40,000 to 50,000 transistors, its application is extremelydifficult in large-scale logic circuits having 10 million gates per chipsuch as a System On Chip (SOC).

[0007] In addition, conventionally, a logic circuit simulator such asthat typified by Verilog-XL or the like is used for logic circuitanalysis. This simulator is able to analyze the logic functions of alarge-scale logic circuit. Nevertheless, while the logic circuitsimulator may be capable of finding the duty of each structural elementconfiguring a logic circuit, for example a primitive cell such as a NANDgate or NOR gate, it is not capable of obtaining the duty of atransistor, for example, a MOS field effect transistor (MOSFET)configuring that primitive gate.

[0008] As described above, it is extremely difficult for a conventionalanalog circuit simulator to obtain the duty of a transistor in alarge-scale logic circuit. Furthermore, a conventional logic circuitsimulator is capable of analyzing a large-scale logic circuit, butcannot obtain the duty of a transistor. In other words, a problem liesin the fact that neither the analog circuit simulator nor the logiccircuit simulator is capable of obtaining the duty of a transistor in alarge-scale logic circuit.

SUMMARY OF THE INVENTION

[0009] An aspect of the present invention provides a system foranalyzing a monolithic integrated circuit. The system includes: a) alogic circuit simulator configured to obtain the duty of a primitivecell that configures a logic circuit to be analyzed by performing alogic simulation of the logic circuit based on a netlist of the logiccircuit and input vectors for the logic circuit; b) an analog circuitsimulator configured to obtain the duty of a transistor that configuresa primitive cell by performing an analog simulation of the primitivecell based on a netlist of the analog circuit of the primitive cell andinput vectors for the primitive cell; and c) a synthesis moduleconfigured to obtain the duty of a transistor of the logic circuit byperforming a synthesis of the duty of the primitive cell and the duty ofthe transistor.

[0010] Another aspect of the present invention provides a method foranalyzing a monolithic integrated circuit. The method includes: a)obtaining the duty of a primitive cell, which configures a logic circuitto be analyzed, by performing a logic simulation of the logic circuitbased on a netlist of the logic circuit and input vectors for the logiccircuit; b) obtaining the duty of a transistor, which configures theprimitive cell, by performing an analog simulation of the primitive cellbased on a netlist of an analog circuit in the primitive cell and inputvectors for the primitive cell; and c) obtaining the duty of atransistor of the logic circuit by performing a synthesis of the duty ofthe primitive cell and the duty of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a diagram showing a configuration of a semiconductorintegrated circuit analysis system according to an embodiment of thepresent invention;

[0012]FIG. 2 is a flowchart of the semiconductor integrated circuitanalysis method according to an embodiment of the present invention;

[0013]FIG. 3A is a diagram showing the bias status of a p-channel MOSFETduring BT stress analysis; and

[0014]FIG. 3B is a diagram showing the bias status of an n-channelMOSFET during BT stress analysis.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Next, embodiments of the present invention are described whilereferencing the drawings. The same or similar reference numerals areused for the same or similar portions in the following description ofthe drawings. However, the drawings are schematic and it should be notedthat that the scale of each measurement may be different from those inactuality.

[0016] (Semiconductor Integrated Circuit Analysis System)

[0017] As shown in FIG. 1, a semiconductor integrated circuit analysissystem according to an embodiment of the present invention includes alogic circuit simulator 1, analog circuit simulator 2 and synthesismodule 3.

[0018] The logic circuit simulator 1 obtains cell duties (the elementactivation rates) 6 of the respective primitive cells of a logic circuitby performing a logic simulation of a logic circuit based on logiccircuit input vectors 5 input during analysis and a netlist 4 of the SOClevel large-scale logic circuit to be analyzed. More specifically, thelogic circuit simulator 1 speculates approximately what percentage ofthe input signal status is assigned to a primitive cell during a unitcycle. Here, “a unit cycle” refers to a designated time period decidedby the designer(s), necessary for the input waveform required for theduty analysis.

[0019] Suppose that, to a primitive cell, for example, to a two-inputNAND gate four combinations of binary input (00, 01, 10, 11) areapplied, in the bias temperature (BT) stress analysis and the timedependent dielectric breakdown (TDDB) analysis, the cell duty of theprimitive cell 6 is defined as the percentage of the period forrespective input signals are applied during the unit cycle. Furthermore,in the hot carrier (HC) analysis, the cell duty 6 of the primitive cellis defined as the probability that an input status will change. Findingthe length of time at each status is sufficient for BT stress analysisand TDDB analysis whereas the rate (percentage) at which each inputstatus transition occurs is important for HC analysis. For example, in atwo-input NAND gate, the four combinations of binary input (00, 01, 10,11) may be as follows: (00 to 01) 10%, (00 to 10) 15%, (00 to 11) 5%,and (01 to 00) 10%.

[0020] The analog circuit simulator 2 performs an analog simulation ofan analog circuit based on a netlist 7 of the analog circuit, whichshows the circuit structure of a primitive cell in the large-scale logiccircuit to be analyzed. And analog circuit input vectors 8, which bringabout a certain specified bias status in transistors configuring theprimitive cell, are input during analysis. Analog simulation is carriedout on a primitive cell that configures the logic circuit. Thetransistor duties 9 of respective transistors configuring the primitivecell are obtained through the results of this analog simulation. Inother words, the percentages of time the respective transistors are at acertain specified bias status during a unit cycle are obtained. Thisspecified bias status is decided arbitrarily in accordance with thedetails of the analysis, for example, the BT stress analysis, TDDBanalysis, or hot carrier analysis.

[0021] The synthesis module 3 obtains the synthesized duty 10 oftransistors at the overall large-scale circuit level by performing asynthesis of the cell duty 6 of the primitive cell obtained using thelogic circuit simulator 1 and the transistor duty 9 of the transistorsobtained using the analog circuit simulator 2. More specifically, thesynthesis module 3 correlates the cell duty 6 of each primitive cell ofthe overall circuit obtained using the logic circuit simulator 1 withthe transistor duties 9 of the respective transistors of thecorresponding primitive cell obtained using the analog circuit simulator2. The synthesis module 3 then calculates the product of the transistorduty when at the specified bias status set for the transistors times thecell duty when input is applied in order to cause the specified bias tobe set for the transistors, and outputs the value of this product as thesynthesized duty 10 at the overall large-scale circuit level.

[0022] Let, for example, “a” be the transistor duty ratio obtained bythe analog circuit simulator 2 where, for example, a transistor Ti of aprimitive cell A at in the set specified bias status during a unitcycle. Meanwhile, let, for example, “b” be the cell duty of theprimitive cell A obtained by the logic circuit simulator 1 when input isapplied in order to cause the specified bias status to be set for thetransistor T1. In this case, the product of the respective duties (a×b)is obtained using the synthesis module 3, and the value of the product(a×b) is applied as the synthesized transistor duty.

[0023] With the analysis system of the semiconductor integrated circuitaccording to this embodiment, the duty cell 6 of each primitive cell isobtained by the logic circuit simulator 1, and the transistor duties 9of respective transistors configuring a primitive cell are obtained bythe analog circuit simulator 2. The respective obtained cell duty 6 andtransistor duties 9 are then synthesized to ultimately obtain the dutysynthesized 10 of the respective transistors at the overall circuitlevel, making it possible to easily obtain the duties of the respectivetransistors in an extremely large-scale circuit such as SOC. Since therealways exists a critical path in a circuit, which is a circuit path thathas timing constraints, the designer(s) may be allowed decide upon whichpath to focus. By performing this analysis solely on these selectedpaths, inspection having favorable design efficiency becomes possible,enabling easier analysis of transistor reliability in the circuit designof the large-scale circuit.

[0024] (Analysis Method for a Semiconductor Integrated Circuit)

[0025] Next, an analysis method for a semiconductor integrated circuitaccording to an embodiment of the present invention is described whilereferencing FIG. 1 and FIG. 2.

[0026] (a) In step S11, logic circuit input vectors 5 to be input duringanalysis and a netlist 4 of a SOC level large-scale logic circuit to beanalyzed are input. In addition, a logic circuit simulator 1 obtains thecell duty (the element activation rate) 6 of each primitive cell of thelogic circuit by performing a logical simulation of a logic circuitbased on the logic circuit netlist 4 and the logic circuit input vectors5. The cell duty 6 of each primitive cell obtained using the logiccircuit simulator 1 is transferred to a synthesis module 3.

[0027] (b) Meanwhile, in step S12, an analog circuit simulator 2receives a analog circuit netlist 7 showing a circuit structure of aprimitive cell in the large-scale circuit to become the analysis targetand analog circuit inputs vectors 8 that bring about a certain specifiedstatus in transistors configuring the primitive cell and are inputduring analysis. In addition, the analog circuit simulator 2 obtains thetransistor duties 9 of the respective transistors configuring theprimitive cell by performing an analog simulation of the analog circuitbased on the analog circuit netlist 7 and the analog circuit inputvectors 8. The transistor duty obtained with the analog circuitsimulator 2 is output to the synthesis module 3.

[0028] (c) Next, in step S13, the synthesis module 3 obtains thesynthesized duty 10 at the overall large-scale logic circuit level byperforming a synthesis of the cell duty 6 of the primitive cell obtainedwith the logic circuit simulator 1 in step Sll and the transistor duty 9of the transistors obtained with the analog circuit simulator 2 in stepS12.

[0029] According to the analysis method for a semiconductor integratedcircuit of the embodiment of the present invention, the cell duty 6 ofeach primitive cell is obtained by the logic circuit simulator 1, andthe transistor duties 9 of the respective transistors configuring theprimitive cell are obtained by the analog circuit simulator 2. Therespective obtained cell duty 6 and transistor duties 9 are synthesizedto ultimately obtain the synthesized duty 10 of the respectivetransistors at the overall circuit level, making it possible to easilyobtain the duties of the transistors in the extremely large-scalecircuit such as SOC.

[0030] (Hot Carrier Analysis)

[0031] Next, the case where the semiconductor integrated circuitanalysis system a according to an embodiment of the present invention isapplied to hot carrier analysis of a MOSFET is described.

[0032] Conventionally, a tool that can handle the problem of a hotcarrier in a MOSFET, for example, a tool called “BERT” is known as atool that uses analog circuit simulation. In addition, a tool named“GLACIER”, for example, is known as a tool that uses logic circuitsimulation.

[0033] In order to analyze the problem of the hot carrier of the MOSFETcorrectly with these tools, the extent to which the MOSFET is in a biasstatus where the injection of a hot carrier may be likely to occurduring operation of the circuit must be estimated correctly. However,with the analog circuit simulator there is a limit to the circuit scalecapable of being analyzed, and the logic circuit simulator has not beencapable of handling the duty at transistor level.

[0034] Therefore, the specified transistor bias status is set to a biasstatus where hot carrier injection is likely to occur. Morespecifically, a bias status where a transistor may be deteriorated by ahot carrier, and change in threshold value (V_(T)) and/or deteriorationof conductance are likely to occur is set. For example, a bias statuswhere V_(GS) (voltage between gate and source) >V_(T) and V_(DS)(voltage between drain and source) ≧V_(GS) is set. The semiconductorintegrated circuit analysis system according to an embodiment of thepresent invention is implemented with such bias status settings.

[0035] With the hot carrier analysis using the semiconductor integratedcircuit analysis system according to an embodiment of the presentinvention, it is possible to obtain the duty of a transistor in an SOClevel large-scale circuit during actual circuit operation, which isnecessary for hot carrier reliability analysis.

[0036] (BT Stress Analysis)

[0037] Next, the case where the semiconductor integrated circuitanalysis system according to the embodiment of the present invention isapplied to BT stress analysis of the MOSFET is described.

[0038] As shown in FIGS. 3A and 3B, in order to make the semiconductorintegrated circuit analysis system shown in FIG. 1 applicable to BTstress analysis, a specified transistor bias status is set to a biasstatus where BT stress may occur in a MOSFET. Namely, in the case of ap-channel MOSFET, as shown in FIG. 3A, the gate potential is set at−V_(dd) (V_(dd)=power supply voltage), and the source potential, thedrain potential and the substrate potential are respectively set at 0 V.In the case of an n-channel MOSFET, as illustrated in FIG. 3B, the gatepotential is set at +V_(dd), and the source potential, the drainpotential and the substrate potential are respectively set at 0 V. Thesemiconductor integrated circuit analysis system according to thisembodiment may be implemented with such bias settings.

[0039] With the BT stress analysis using the semiconductor integratedcircuit analysis system according to an embodiment of the presentinvention, it is possible to obtain the duty of a transistor in an SOClevel large-scale circuit during actual circuit operation, which isnecessary for BT stress reliability analysis.

[0040] (TDDB Analysis)

[0041] Next, the case where the semiconductor integrated circuitanalysis system according to an embodiment of the present invention isapplied to TDDB analysis of the MOSFET is described.

[0042] The TDDB characteristics of a MOSFET are obtained as a functionof the surface area of the gate oxide film and the applied voltage tothe gate terminal. Accordingly, in order to make the semiconductorintegrated circuit analysis system according to the embodiment shown inFIG. 1 applicable to TDDB analysis, the specified transistor bias statusis set to the bias status where a gate voltage equal to or greater thanthe power supply voltage is applied to the gate terminal during a unitcycle. The semiconductor integrated circuit analysis system according toan embodiment of the present invention is implemented with suchsettings.

[0043] With the TDDB analysis using the semiconductor integrated circuitanalysis system according to an embodiment of the present invention, itis possible to obtain the duty of a transistor in an SOC levellarge-scale circuit during actual circuit operation, which is requiredfor TDDB reliability analysis, from the area of the gate oxide filmobtained from transistor layout data and the results of analysis systemimplementation.

[0044] As described above, with the semiconductor integrated circuitanalysis system and the analysis method of the same according to anembodiment of the present invention, since the duty of a transistor atthe overall circuit level may be obtained through the synthesis of thecell duty of a primitive cell obtained by the logic circuit simulatorand the transistor duty of the transistor configuring the primitive cellobtained by the analog circuit simulator, the synthesized duty of atransistor in a large-scale logic circuit may be easily obtained.

[0045] In the preceding, the present invention has been described indetail by means of embodiments; however, it will become clear to thoseskilled in the art that the present invention is not limited to theembodiments described in this application. For example, the above wasdescribed using a MOSFET, but a junction type FET, Schottky gate FET(MESFET), high electron mobility transistor (HEMT), bipolar transistor(BJT), or static induction transistor (SIT) may be used as well.

[0046] The apparatus of the present invention may be implemented withvarious corrections and modifications without falling outside of thespirit and scope of the present invention as laid out by the patentclaims. Accordingly, the description included in this application isintended to be an exemplary description, and is not meant to beconstrued as limiting the present invention in any manner.

What is claimed is:
 1. A system for analyzing a monolithic integratedcircuit, comprising: a logic circuit simulator configured to obtain acell duty of a primitive cell configuring a logic circuit by performinga logic simulation of the logic circuit based on a netlist of the logiccircuit and input vectors for the logic circuit; an analog circuitsimulator configured to obtain a transistor duty of a transistorconfiguring the primitive cell by performing an analog simulation of theprimitive cell based on a netlist in the analog circuit of the primitivecell and input vectors for the primitive cell; and a synthesis moduleconfigured to obtain a synthesized duty of the transistor of the logiccircuit by performing a synthesis of the cell and transistor.
 2. Thesystem of claim 1, wherein the synthesis by the synthesis modulecalculates the product of the transistor duty when at a specified biasstatus set for the transistor and the cell duty of the primitive cellthat is applied an input to cause the specified bias status to be set.3. The system of claim 2, wherein the specified bias status for thetransistor is set to a bias status where the injection of a hot carrieroccurs in the transistor.
 4. The system of claim 3, wherein in thetransistor, the voltage between the gate and the source is set to belarger than a threshold value, and the voltage between the drain and thesource is set to be equal to or greater than that between the gate andthe source.
 5. The system of claim 2, wherein the specified bias statusof the transistor is set to a bias status where BT stress occurs in thetransistor.
 6. The system of claim 5, wherein if the transistor is ap-channel MOSFET, the gate potential is set at a negative power supplyvoltage, and the source potential, drain potential and substratepotential are respectively set at 0 V.
 7. The system of claim 5, whereinthe transistor is an n-channel MOSFET, the gate potential is set at apositive power supply voltage, and the source potential, drain potentialand substrate potential are respectively set at 0 V.
 8. The system ofclaim 2, wherein in the transistor, the gate potential is set to beequal to or greater than the power supply voltage.
 9. A method foranalyzing a monolithic integrated circuit, comprising: obtaining a cellduty of a primitive cell configuring a logic circuit by performing alogic simulation of the logic circuit based on a netlist of the logiccircuit and input vectors for the logic circuit; obtaining a transistorduty of a transistor configuring the primitive cell, by performing ananalog simulation of the primitive cell based on a netlist of an analogcircuit in the primitive cell and input vectors for the primitive cell;and obtaining a synthesized duty of a transistor of the logic circuit byperforming a synthesis of the cell and transistor.
 10. The method ofclaim 9, wherein the synthesis is configured to calculate the product ofthe transistor duty in a specified bias status set for the transistorand the cell duty of a primitive cell that is applied an input to causethe specified bias status.
 11. The method of claim 10, wherein thespecified bias status of the transistor is set to a bias status wherethe injection of a hot carrier occurs in the transistor.
 12. The methodof claim 11, wherein in the transistor, the voltage between the gate andthe source is set to be larger than a threshold value, and voltagebetween the drain and the source is set to be equal to or greater thanthat between the gate and the source.
 13. The method of claim 10,wherein the specified bias status of the transistor is set to a biasstatus where BT stress may occur in the transistor.
 14. The method ofclaim 13, wherein the transistor is a p-channel MOSFET, the gatepotential is set at a negative power supply voltage, and the sourcepotential, drain potential and substrate potential are respectively setat 0 V.
 15. The method of claim 13, wherein the transistor is ann-channel MOSFET, the gate potential is set at a positive power supplyvoltage, and the source potential, drain potential and substratepotential are respectively set at 0 V.
 16. The method of claim 10,wherein in the transistor, the gate potential is set larger than powersupply voltage.